The present invention relates to a method for fabricating high-density VLSI device structures.
The incessant trend towards smaller device geometries is ceasing to produce major area economies in the density of entire integrated circuits, because the isolation technologies currently used do not scale advantageously. LOCOS isolation creates a bird's-beak region around the periphery of every moat, and the width of this bird's-beak region is dependent only on the thickness of the field oxide. For a given operation voltage, the oxide thickness must remain at a certain minimum height to maintain sufficient field thresholds, so as to prevent formation of parasitic channels underneath the field oxide. Thus, for a given voltage of operation, the scalability of LOCOS is inherently limited. Therefore, a new and different isolation scheme is essential to achieve true very large scale integration.
One possibility for a new isolation technology is direct moat isolation. The merits of and the need for direct moat isolation are extensively discussed in U.S. patent application Ser. No. 353,992, simultaneously filed and of common assignee with the present application, which is hereby incorporated by reference. In addition, the drawings in the Parillo et al paper presented at the 1980 IEDM as Paper No. 29.1, appear to rely on use of some variant of a direct moat isolation scheme.
Direct moat isolation permits a single implant everywhere to serve a dual function. In the thick oxide regions, it serves as a channel stop implant, whereas in the active device area, it serves as a deep channel implant for punchthrough protection. Additional channel implants are performed to adjust the threshold voltage (V.sub.T) of active devices. The higher doping in the channel, compared to the channel stop, is justified for a 1-micron technology because it can be shown that the dopant concentration (assumed to be uniform for simplicity) of the channel stop (N.sub.A,Thick) and the dopant concentration of the active device region (N.sub.A,Thin) can be related to the field oxide thickness (d.sub.Thick) and gate oxide thickness (d.sub.Thin) as follows (assuming V.sub.T,Thin =0.5 V, V.sub.T,Thick &lt;10 V, interface charge density N.sub.f =5.times.10.sup.10 cm.sup.-2, and ignoring short channel effects) ##EQU1## For d.sub.Thin =250 Angstroms and d.sub.Thick =5500 Angstroms, this means that EQU N.sub.A,Thick /N.sub.A,Thin &gt;0.46
Thus, unlike earlier n-channel implementations which required N.sub.a,Thick &gt;N.sub.A,Thin (and in fact required the invention of LOCOS to accomplish this), scaled technologies are less restrictive. Therefore, the continuity of the combined channel-stop/punchthrough implant at the edge of the channel width will reduce the lateral doping non-uniformity resulting in reduced electrical encroachment of the channel width. Furthermore, because of the etching process used in the direct moat isolation, the active area is not encroached upon by the field oxide as in the case of LOCOS. Therefore, the direct moat isolation enables more efficient usage of the silicon area by allowing closer packing of active devices than the LOCOS.
Other proposals for new isolation schemes include, e.g., the fully framed fully recessed oxide approach using sidewall nitride, published in 127 J. Electrochem. Soc. 2468 (1980), and the proposed recessed oxide by liftoff approach, presented by Kurosawa et al at the 1981 Device Research Conference.
Most approaches other than direct moat isolation involve complex processing and thus have very questionable cost effectiveness. Most of these approaches, except possibly the F.sup.3 R approach, still leave moat encroachments of less than a half micron very difficult to achieve.
However, a difficulty with direct moat isolation is that step coverage of the moat sidewalls becomes a problem. This is not a difficulty in LOCOS, because the moat encroachment naturally leads to a tapered oxide geometry. The direct moat isolation process disclosed in copending application Ser. No. 353,992 provides a direct moat isolation process which also achieves control of the oxide sidewall slope. However, a process which imposes a maximum sidewall slope not only imposes additional constraints on processing (and therefore lower yield), but also may not take full advantage of the compact isolation which is possible.
Thus, it is an object of the present invention to provide a method for fabricating VLSI devices using direct moat isolation which does not impose any constraint on sidewall slope.
It is a further object of the present invention to provide a process for fabricating VLSI devices using direct moat isolation with near-vertical oxide sidewalls.
It is a further object of the present invention to provide a process for fabricating VLSI devices using direct moat isolation with minimal process complexity.